On completely robust path delay fault testable realization of logic functions
نویسنده
چکیده
A large class of Boolean functions, as well as almost all symmetr ic Boolean functions, are shown to have no two-level completely robust path-delay-fault testable ( R P D F T ) realization b y combinational circuits. Exact and asymptotic formulae are derived fo r the number of symmetric Boolean functions which have two-level completely R P D F T realization. To achieve completely R P D F T realization, a notion of RPDFT-ex tens ion as proposed f o r logic functions which have no two-level completely R P D F T realization. Algorithms are de vised fo r the design o f RPDFT-extensions with at most 2 extra input variables.
منابع مشابه
Synthesis of robust delay-fault-testable circuits: theory
Correct operation of synchronous digital circuits requires propagation delays of all sensitizable paths in the circuit to be smaller than a speciied limit. Physical defects and processing variations in integrated circuits can aaect the temporal behavior of a circuit without altering the logical behavior. These defects are called delay faults. In order to design, and especially to synthesize, hi...
متن کاملTO APPEAR IN IEEE TRANSACTIONS ON COMPUTERSA Study of Theoretical Issues in the Synthesis of Delay Fault Testable Circuits 1
Multilevel Logic Optimization Transformations used in existing logic synthesis systems are characterized with respect to their testability preserving and testability enhancing properties. A su cient condition for a multilevel unate circuit to be \hazard free delay fault testable" is presented. In contrast to existing results that consider either \single path propagating hazard free robust tests...
متن کاملA Fast Optimal Robust Path Delay Fault Testable
In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of (n 2) for the cardi-nality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O(p n)-time adder that is fully robust path delay fault testable with a test set...
متن کاملSynthesis of asynchronous circuits for stuck-at and robust path delay fault testability
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free and completely testable. Making an asynchronous two-level circuit hazard-free usually requires the introduction of either redundant or non-prime cubes, or both. This adversely a ects its testability. However, using extra inputs, which is seldom necessary, and a synthesis for testability m...
متن کاملUniversal delay test sets for logic networks
| It has been shown earlier that, if we restrict to unate gate network (UGN) realizations, there exist universal test sets for boolean functions. Such a test set only depends on the function f , and checks any UGN realization of f for all multiple stuck-at faults and all robustly testable stuck-open faults. In this paper we prove that these universal test sets are much more powerful than implie...
متن کامل